/*
** ###################################################################
**     Processors:          KW45B41Z52AFPA
**                          KW45B41Z52AFTA
**                          KW45B41Z53AFPA
**                          KW45B41Z53AFTA
**                          KW45B41Z82AFPA
**                          KW45B41Z82AFTA
**                          KW45B41Z83AFPA
**                          KW45B41Z83AFPA_NBU
**                          KW45B41Z83AFTA
**                          KW45B41Z83AFTA_NBU
**                          KW45Z41052AFPA
**                          KW45Z41052AFTA
**                          KW45Z41053AFPA
**                          KW45Z41053AFTA
**                          KW45Z41082AFPA
**                          KW45Z41082AFTA
**                          KW45Z41083AFPA
**                          KW45Z41083AFTA
**
**     Version:             rev. 1.0, 2020-05-12
**     Build:               b240715
**
**     Abstract:
**         CMSIS Peripheral Access Layer for XCVR_TX_DIG
**
**     Copyright 1997-2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2024 NXP
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
**     Revisions:
**     - rev. 1.0 (2020-05-12)
**         Initial version.
**
** ###################################################################
*/

/*!
 * @file XCVR_TX_DIG.h
 * @version 1.0
 * @date 2020-05-12
 * @brief CMSIS Peripheral Access Layer for XCVR_TX_DIG
 *
 * CMSIS Peripheral Access Layer for XCVR_TX_DIG
 */

#if !defined(XCVR_TX_DIG_H_)
#define XCVR_TX_DIG_H_                           /**< Symbol preventing repeated inclusion */

#if (defined(CPU_KW45B41Z52AFPA) || defined(CPU_KW45B41Z52AFTA))
#include "KW45B41Z52_COMMON.h"
#elif (defined(CPU_KW45B41Z53AFPA) || defined(CPU_KW45B41Z53AFTA))
#include "KW45B41Z53_COMMON.h"
#elif (defined(CPU_KW45B41Z82AFPA) || defined(CPU_KW45B41Z82AFTA))
#include "KW45B41Z82_COMMON.h"
#elif (defined(CPU_KW45B41Z83AFPA) || defined(CPU_KW45B41Z83AFTA))
#include "KW45B41Z83_COMMON.h"
#elif (defined(CPU_KW45B41Z83AFPA_NBU) || defined(CPU_KW45B41Z83AFTA_NBU))
#include "KW45B41Z83_NBU_COMMON.h"
#elif (defined(CPU_KW45Z41052AFPA) || defined(CPU_KW45Z41052AFTA))
#include "KW45Z41052_COMMON.h"
#elif (defined(CPU_KW45Z41053AFPA) || defined(CPU_KW45Z41053AFTA))
#include "KW45Z41053_COMMON.h"
#elif (defined(CPU_KW45Z41082AFPA) || defined(CPU_KW45Z41082AFTA))
#include "KW45Z41082_COMMON.h"
#elif (defined(CPU_KW45Z41083AFPA) || defined(CPU_KW45Z41083AFTA))
#include "KW45Z41083_COMMON.h"
#else
  #error "No valid CPU defined!"
#endif

/* ----------------------------------------------------------------------------
   -- Device Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
 * @{
 */


/*
** Start of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic push
  #else
    #pragma push
    #pragma anon_unions
  #endif
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=extended
#else
  #error Not supported compiler type
#endif

/* ----------------------------------------------------------------------------
   -- XCVR_TX_DIG Peripheral Access Layer
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer
 * @{
 */

/** XCVR_TX_DIG - Register Layout Typedef */
typedef struct {
  __IO uint32_t TXDIG_CTRL;                        /**< TXDIG_CTRL, offset: 0x0 */
  __IO uint32_t DATA_PADDING_CTRL;                 /**< DATA_PADDING_CTRL, offset: 0x4 */
  __IO uint32_t DATA_PADDING_CTRL_1;               /**< DATA_PADDING_CTRL_1, offset: 0x8 */
  __IO uint32_t DATA_PADDING_CTRL_2;               /**< DATA_PADDING_CTRL_2, offset: 0xC */
  __IO uint32_t FSK_CTRL;                          /**< FSK_CTRL, offset: 0x10 */
  __IO uint32_t GFSK_CTRL;                         /**< GFSK_CTRL, offset: 0x14 */
  __IO uint32_t GFSK_COEFF_0_1;                    /**< GFSK_COEFF_0_1, offset: 0x18 */
  __IO uint32_t GFSK_COEFF_2_3;                    /**< GFSK_COEFF_2_3, offset: 0x1C */
  __IO uint32_t GFSK_COEFF_4_5;                    /**< GFSK_COEFF_4_5, offset: 0x20 */
  __IO uint32_t GFSK_COEFF_6_7;                    /**< GFSK_COEFF_6_7, offset: 0x24 */
  __IO uint32_t IMAGE_FILTER_CTRL;                 /**< IMAGE_FILTER_CTRL, offset: 0x28 */
  __IO uint32_t PA_CTRL;                           /**< PA_CTRL, offset: 0x2C */
  __IO uint32_t PA_RAMP_TBL0;                      /**< PA_RAMP_TBL0, offset: 0x30 */
  __IO uint32_t PA_RAMP_TBL1;                      /**< PA_RAMP_TBL1, offset: 0x34 */
  __IO uint32_t PA_RAMP_TBL2;                      /**< PA_RAMP_TBL2, offset: 0x38 */
  __IO uint32_t PA_RAMP_TBL3;                      /**< PA_RAMP_TBL3, offset: 0x3C */
  __IO uint32_t SWITCH_TX_CTRL;                    /**< SWITCH_TX_CTRL, offset: 0x40 */
  __IO uint32_t RF_DFT_TX_CTRL0;                   /**< RF_DFT_TX_CTRL0, offset: 0x44 */
  __IO uint32_t RF_DFT_TX_CTRL1;                   /**< RF_DFT_TX_CTRL1, offset: 0x48 */
  __IO uint32_t RF_DFT_TX_CTRL2;                   /**< RF_DFT_TX_CTRL2, offset: 0x4C */
  __IO uint32_t RF_DFT_PATTERN;                    /**< RF_DFT_PATTERN, offset: 0x50 */
  __IO uint32_t DATARATE_CONFIG_FSK_CTRL;          /**< DATARATE_CONFIG_FSK_CTRL, offset: 0x54 */
  __IO uint32_t DATARATE_CONFIG_GFSK_CTRL;         /**< DATARATE_CONFIG_GFSK_CTRL, offset: 0x58 */
  __IO uint32_t DATARATE_CONFIG_FILTER_CTRL;       /**< DATARATE_CONFIG_FILTER_CTRL, offset: 0x5C */
} XCVR_TX_DIG_Type;

/* ----------------------------------------------------------------------------
   -- XCVR_TX_DIG Register Masks
   ---------------------------------------------------------------------------- */

/*!
 * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks
 * @{
 */

/*! @name TXDIG_CTRL - TXDIG_CTRL */
/*! @{ */

#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_MASK (0x1U)
#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_SHIFT (0U)
/*! MODULATOR_SEL - MODULATOR_SEL */
#define XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_MODULATOR_SEL_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_MASK       (0x2U)
#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_SHIFT      (1U)
/*! PFC_EN - PFC_EN */
#define XCVR_TX_DIG_TXDIG_CTRL_PFC_EN(x)         (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_PFC_EN_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_MASK (0x4U)
#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_SHIFT (2U)
/*! DATA_STREAM_SEL - DATA_STREAM_SEL */
#define XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_DATA_STREAM_SEL_MASK)

#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_MASK (0x10U)
#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_SHIFT (4U)
/*! INV_DATA_OUT - INV_DATA_OUT */
#define XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_SHIFT)) & XCVR_TX_DIG_TXDIG_CTRL_INV_DATA_OUT_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL - DATA_PADDING_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_MASK (0x3U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_SHIFT (0U)
/*! DATA_PADDING_SEL - DATA_PADDING_SEL */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_DATA_PADDING_SEL_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_MASK (0x4U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_SHIFT (2U)
/*! TX_CAPTURE_POL - TX_CAPTURE_POL */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_TX_CAPTURE_POL_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_MASK (0x10U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_SHIFT (4U)
/*! CTE_DATA - CTE_DATA */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_CTE_DATA_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_MASK (0xF00U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_SHIFT (8U)
/*! PAD_DLY - PAD_DLY */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_MASK (0x1000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_SHIFT (12U)
/*! PAD_DLY_EN - PAD_DLY_EN */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_PAD_DLY_EN_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_MASK (0x10000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_SHIFT (16U)
/*! RAMP_DN_PAD_EN - RAMP_DN_PAD_EN */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_RAMP_DN_PAD_EN_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL_1 - DATA_PADDING_CTRL_1 */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_MASK (0x1FU)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_SHIFT (0U)
/*! RAMP_UP_DLY - RAMP_UP_DLY */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_RAMP_UP_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_MASK (0x700U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_SHIFT (8U)
/*! TX_DATA_FLUSH_DLY - TX_DATA_FLUSH_DLY */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_TX_DATA_FLUSH_DLY_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_MASK (0xF000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_SHIFT (12U)
/*! PA_PUP_ADJ - PA_PUP_ADJ */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_1_PA_PUP_ADJ_MASK)
/*! @} */

/*! @name DATA_PADDING_CTRL_2 - DATA_PADDING_CTRL_2 */
/*! @{ */

#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_MASK (0x1FFFU)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_SHIFT (0U)
/*! DATA_PAD_MFDEV - DATA_PAD_MFDEV */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_MFDEV_MASK)

#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_MASK (0x1FFF0000U)
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_SHIFT (16U)
/*! DATA_PAD_PFDEV - DATA_PAD_PFDEV */
#define XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_CTRL_2_DATA_PAD_PFDEV_MASK)
/*! @} */

/*! @name FSK_CTRL - FSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_MASK     (0x1FFFU)
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_SHIFT    (0U)
/*! FSK_FDEV_0 - FSK_FDEV_0 */
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_SHIFT)) & XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_0_MASK)

#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_MASK     (0x1FFF0000U)
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_SHIFT    (16U)
/*! FSK_FDEV_1 - FSK_FDEV_1 */
#define XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_SHIFT)) & XCVR_TX_DIG_FSK_CTRL_FSK_FDEV_1_MASK)
/*! @} */

/*! @name GFSK_CTRL - GFSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_MASK     (0xFFFU)
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_SHIFT    (0U)
/*! GFSK_FDEV - GFSK_FDEV */
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FDEV_MASK)

#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_MASK (0x1000U)
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_SHIFT (12U)
/*! GFSK_COEFF_MAN - GFSK_COEFF_MAN */
#define XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_COEFF_MAN_MASK)

#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_MASK (0x10000U)
#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_SHIFT (16U)
/*! BT_EQ_OR_GTR_ONE - BT_EQ_OR_GTR_ONE */
#define XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_BT_EQ_OR_GTR_ONE_MASK)
/*! @} */

/*! @name GFSK_COEFF_0_1 - GFSK_COEFF_0_1 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_SHIFT (0U)
/*! GFSK_COEFF_0 - GFSK_COEFF_0 */
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_0_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_SHIFT (16U)
/*! GFSK_COEFF_1 - GFSK_COEFF_1 */
#define XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_0_1_GFSK_COEFF_1_MASK)
/*! @} */

/*! @name GFSK_COEFF_2_3 - GFSK_COEFF_2_3 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_SHIFT (0U)
/*! GFSK_COEFF_2 - GFSK_COEFF_2 */
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_2_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_SHIFT (16U)
/*! GFSK_COEFF_3 - GFSK_COEFF_3 */
#define XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_2_3_GFSK_COEFF_3_MASK)
/*! @} */

/*! @name GFSK_COEFF_4_5 - GFSK_COEFF_4_5 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_SHIFT (0U)
/*! GFSK_COEFF_4 - GFSK_COEFF_4 */
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_4_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_SHIFT (16U)
/*! GFSK_COEFF_5 - GFSK_COEFF_5 */
#define XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_4_5_GFSK_COEFF_5_MASK)
/*! @} */

/*! @name GFSK_COEFF_6_7 - GFSK_COEFF_6_7 */
/*! @{ */

#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_MASK (0x1FFU)
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_SHIFT (0U)
/*! GFSK_COEFF_6 - GFSK_COEFF_6 */
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_6_MASK)

#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_MASK (0x1FF0000U)
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_SHIFT (16U)
/*! GFSK_COEFF_7 - GFSK_COEFF_7 */
#define XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF_6_7_GFSK_COEFF_7_MASK)
/*! @} */

/*! @name IMAGE_FILTER_CTRL - IMAGE_FILTER_CTRL */
/*! @{ */

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_MASK (0x3U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_SHIFT (0U)
/*! IMAGE_FIR_FILTER_SEL - IMAGE_FIR_FILTER_SEL */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_SEL_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_MASK (0x4U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_SHIFT (2U)
/*! IMAGE_FILTER_OVRD_EN - IMAGE_FILTER_OVRD_EN */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FILTER_OVRD_EN_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_MASK (0x8U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_SHIFT (3U)
/*! IMAGE_FIR_FILTER_OVRD - IMAGE_FIR_FILTER_OVRD */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_FIR_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_MASK (0x10U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_SHIFT (4U)
/*! IMAGE_SYNC1_FILTER_OVRD - IMAGE_SYNC1_FILTER_OVRD */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC1_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_MASK (0x20U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_SHIFT (5U)
/*! IMAGE_SYNC0_FILTER_OVRD - IMAGE_SYNC0_FILTER_OVRD */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_IMAGE_SYNC0_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_MASK (0x3FF0000U)
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_SHIFT (16U)
/*! FREQ_WORD_ADJ - FREQ_WORD_ADJ */
#define XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_IMAGE_FILTER_CTRL_FREQ_WORD_ADJ_MASK)
/*! @} */

/*! @name PA_CTRL - PA_CTRL */
/*! @{ */

#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_MASK    (0x3FU)
#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_SHIFT   (0U)
/*! PA_TGT_POWER - PA_TGT_POWER */
#define XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER(x)      (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_SHIFT)) & XCVR_TX_DIG_PA_CTRL_PA_TGT_POWER_MASK)

#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_MASK     (0x100U)
#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_SHIFT    (8U)
/*! TGT_PWR_SRC - TGT_PWR_SRC */
#define XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TGT_PWR_SRC_MASK)

#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_MASK (0x1000U)
#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_SHIFT (12U)
/*! EARLY_WU_COMPLETE - EARLY_WU_COMPLETE */
#define XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_SHIFT)) & XCVR_TX_DIG_PA_CTRL_EARLY_WU_COMPLETE_MASK)

#define XCVR_TX_DIG_PA_CTRL_RAMP_CS_MASK         (0xE000U)
#define XCVR_TX_DIG_PA_CTRL_RAMP_CS_SHIFT        (13U)
/*! RAMP_CS - RAMP_CS */
#define XCVR_TX_DIG_PA_CTRL_RAMP_CS(x)           (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_RAMP_CS_SHIFT)) & XCVR_TX_DIG_PA_CTRL_RAMP_CS_MASK)

#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_MASK     (0x30000U)
#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_SHIFT    (16U)
/*! PA_RAMP_SEL - PA_RAMP_SEL */
#define XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TX_DIG_PA_CTRL_PA_RAMP_SEL_MASK)

#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_MASK  (0x40000000U)
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_SHIFT (30U)
/*! TX_PA_PUP_OVRD - TX_PA_PUP_OVRD */
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_MASK)

#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_SHIFT (31U)
/*! TX_PA_PUP_OVRD_EN - TX_PA_PUP_OVRD_EN */
#define XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_SHIFT)) & XCVR_TX_DIG_PA_CTRL_TX_PA_PUP_OVRD_EN_MASK)
/*! @} */

/*! @name PA_RAMP_TBL0 - PA_RAMP_TBL0 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_SHIFT  (0U)
/*! PA_RAMP0 - PA_RAMP0 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP0_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_SHIFT  (8U)
/*! PA_RAMP1 - PA_RAMP1 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP1_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_MASK   (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_SHIFT  (16U)
/*! PA_RAMP2 - PA_RAMP2 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP2_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_MASK   (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_SHIFT  (24U)
/*! PA_RAMP3 - PA_RAMP3 */
#define XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL0_PA_RAMP3_MASK)
/*! @} */

/*! @name PA_RAMP_TBL1 - PA_RAMP_TBL1 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_SHIFT  (0U)
/*! PA_RAMP4 - PA_RAMP4 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP4_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_SHIFT  (8U)
/*! PA_RAMP5 - PA_RAMP5 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP5_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_MASK   (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_SHIFT  (16U)
/*! PA_RAMP6 - PA_RAMP6 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP6_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_MASK   (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_SHIFT  (24U)
/*! PA_RAMP7 - PA_RAMP7 */
#define XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL1_PA_RAMP7_MASK)
/*! @} */

/*! @name PA_RAMP_TBL2 - PA_RAMP_TBL2 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_MASK   (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_SHIFT  (0U)
/*! PA_RAMP8 - PA_RAMP8 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP8_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_MASK   (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_SHIFT  (8U)
/*! PA_RAMP9 - PA_RAMP9 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9(x)     (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP9_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_MASK  (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_SHIFT (16U)
/*! PA_RAMP10 - PA_RAMP10 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP10_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_MASK  (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_SHIFT (24U)
/*! PA_RAMP11 - PA_RAMP11 */
#define XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL2_PA_RAMP11_MASK)
/*! @} */

/*! @name PA_RAMP_TBL3 - PA_RAMP_TBL3 */
/*! @{ */

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_MASK  (0x3FU)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_SHIFT (0U)
/*! PA_RAMP12 - PA_RAMP12 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP12_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_MASK  (0x3F00U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_SHIFT (8U)
/*! PA_RAMP13 - PA_RAMP13 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP13_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_MASK  (0x3F0000U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_SHIFT (16U)
/*! PA_RAMP14 - PA_RAMP14 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP14_MASK)

#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_MASK  (0x3F000000U)
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_SHIFT (24U)
/*! PA_RAMP15 - PA_RAMP15 */
#define XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15(x)    (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_SHIFT)) & XCVR_TX_DIG_PA_RAMP_TBL3_PA_RAMP15_MASK)
/*! @} */

/*! @name SWITCH_TX_CTRL - SWITCH_TX_CTRL */
/*! @{ */

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_MASK (0x1U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_SHIFT (0U)
/*! SWITCH_MOD - SWITCH_MOD */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_MOD_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_MASK (0x6U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_SHIFT (1U)
/*! SWITCH_FIR_SEL - SWITCH_FIR_SEL */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_FIR_SEL_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_MASK (0x8U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_SHIFT (3U)
/*! SWITCH_GFSK_COEFF - SWITCH_GFSK_COEFF */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_GFSK_COEFF_MASK)

#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_MASK (0x3F00U)
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_SHIFT (8U)
/*! SWITCH_TGT_PWR - SWITCH_TGT_PWR */
#define XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_SHIFT)) & XCVR_TX_DIG_SWITCH_TX_CTRL_SWITCH_TGT_PWR_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL0 - RF_DFT_TX_CTRL0 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_MASK (0x7FFFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_SHIFT (0U)
/*! DFT_MAX_RAM_SIZE - DFT_MAX_RAM_SIZE */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_MAX_RAM_SIZE_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_MASK (0x7FFF0000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_SHIFT (16U)
/*! DFT_RAM_BASE_ADDR - DFT_RAM_BASE_ADDR */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_BASE_ADDR_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_SHIFT (31U)
/*! DFT_RAM_EN - DFT_RAM_EN */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL0_DFT_RAM_EN_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL1 - RF_DFT_TX_CTRL1 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_MASK (0x1FFFFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_SHIFT (0U)
/*! LFSR_OUT - LFSR_OUT */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT(x)  (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_OUT_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_MASK (0x7000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_SHIFT (24U)
/*! LFSR_CLK_SEL - LFSR_CLK_SEL */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_CLK_SEL_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_MASK (0x38000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_SHIFT (27U)
/*! LFSR_LENGTH - LFSR_LENGTH */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_LENGTH_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_MASK     (0x40000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_SHIFT    (30U)
/*! LRM - LRM */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM(x)       (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LRM_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_SHIFT (31U)
/*! LFSR_EN - LFSR_EN */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN(x)   (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL1_LFSR_EN_MASK)
/*! @} */

/*! @name RF_DFT_TX_CTRL2 - RF_DFT_TX_CTRL2 */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_MASK (0xFU)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_SHIFT (0U)
/*! DFT_PA_AM_MOD_FREQ - DFT_PA_AM_MOD_FREQ */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_FREQ_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_MASK (0xF0U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_SHIFT (4U)
/*! DFT_PA_AM_MOD_ENTRIES - DFT_PA_AM_MOD_ENTRIES */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_ENTRIES_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_MASK (0x100U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_SHIFT (8U)
/*! DFT_PA_AM_MOD_EN - DFT_PA_AM_MOD_EN */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PA_AM_MOD_EN_MASK)

#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_MASK (0x80000000U)
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_SHIFT (31U)
/*! DFT_PATTERN_EN - DFT_PATTERN_EN */
#define XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_TX_CTRL2_DFT_PATTERN_EN_MASK)
/*! @} */

/*! @name RF_DFT_PATTERN - RF_DFT_PATTERN */
/*! @{ */

#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU)
#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U)
/*! DFT_MOD_PATTERN - DFT_MOD_PATTERN */
#define XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_RF_DFT_PATTERN_DFT_MOD_PATTERN_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_FSK_CTRL - DATARATE_CONFIG_FSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_MASK (0x1FFFU)
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_SHIFT (0U)
/*! DATARATE_CONFIG_FSK_FDEV0 - DATARATE_CONFIG_DATA_PAD_MFDEV */
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV0_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_MASK (0x1FFF0000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_SHIFT (16U)
/*! DATARATE_CONFIG_FSK_FDEV1 - DATARATE_CONFIG_DATA_PAD_PFDEV */
#define XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FSK_CTRL_DATARATE_CONFIG_FSK_FDEV1_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_GFSK_CTRL - DATARATE_CONFIG_GFSK_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_MASK (0xFFFU)
#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_SHIFT (0U)
/*! DATARATE_CONFIG_GFSK_FDEV - DATARATE_CONFIG_GFSK_FDEV */
#define XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_GFSK_CTRL_DATARATE_CONFIG_GFSK_FDEV_MASK)
/*! @} */

/*! @name DATARATE_CONFIG_FILTER_CTRL - DATARATE_CONFIG_FILTER_CTRL */
/*! @{ */

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_MASK (0x1U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_SHIFT (0U)
/*! DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN - DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FILTER_OVRD_EN_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_MASK (0x2U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_SHIFT (1U)
/*! DATARATE_CONFIG_FIR_FILTER_OVRD - DATARATE_CONFIG_FIR_FILTER_OVRD */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_FIR_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_MASK (0x4U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_SHIFT (2U)
/*! DATARATE_CONFIG_SYNC0_FILTER_OVRD - DATARATE_CONFIG_SYNC0_FILTER_OVRD */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_MASK (0x8U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_SHIFT (3U)
/*! DATARATE_CONFIG_SYNC1_FILTER_OVRD - DATARATE_CONFIG_SYNC1_FILTER_OVRD */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_FILTER_OVRD_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_MASK (0x70000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_SHIFT (16U)
/*! DATARATE_CONFIG_GFSK_FILT_CLK_SEL - DATARATE_CONFIG_GFSK_FILT_CLK_SEL */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_GFSK_FILT_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_MASK (0x700000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_SHIFT (20U)
/*! DATARATE_CONFIG_SYNC0_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC0_CLK_SEL */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC0_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_MASK (0x7000000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_SHIFT (24U)
/*! DATARATE_CONFIG_SYNC1_CLK_SEL - DATARATE_CONFIG_IMAGE_SYNC1_CLK_SEL */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_SYNC1_CLK_SEL_MASK)

#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_MASK (0x10000000U)
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_SHIFT (28U)
/*! DATARATE_CONFIG_IMAGE_FIR_CLK_SEL - DATARATE_CONFIG_IMAGE_FIR_CLK_SEL */
#define XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_SHIFT)) & XCVR_TX_DIG_DATARATE_CONFIG_FILTER_CTRL_DATARATE_CONFIG_IMAGE_FIR_CLK_SEL_MASK)
/*! @} */


/*!
 * @}
 */ /* end of group XCVR_TX_DIG_Register_Masks */


/*!
 * @}
 */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */


/*
** End of section using anonymous unions
*/

#if defined(__ARMCC_VERSION)
  #if (__ARMCC_VERSION >= 6010050)
    #pragma clang diagnostic pop
  #else
    #pragma pop
  #endif
#elif defined(__GNUC__)
  /* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
  #pragma language=default
#else
  #error Not supported compiler type
#endif

/*!
 * @}
 */ /* end of group Peripheral_access_layer */


#endif  /* XCVR_TX_DIG_H_ */

